A TSV provides communication links between dies in a vertical direction and is a critical design issue in 3D integration. Similar to other components of a 3D integrated circuit (IC) stack, the fabrication and bonding of TSVs can fail. A failed TSV can severely increase cost and decrease yield as the number of dies to be stacked increases.
A known approach to solve this problem involves using a switching box in a 3D dynamic random-access memory (DRAM) design where for every four signal TSVs there are two redundant TSVs, i.e., 50% TSV redundancy. This approach works where the delay in all of the TSVs are identical; however, this approach takes up more space on the die and is not a cost effective solution for application-specific integrated circuit (ASIC) applications. A second known approach involves a fault tolerant scheme for a 3-D network on chip (3-DNoC) where there are four redundant TSVs for every 38 signal TSVs (32 I/O+6 control signals). This approach makes assumptions such as 100,000 TSVs form a chain, and there are 9.87 defects per million opportunities. Even though the yield improves from 68% to 98%, this assumption does not hold true for other designs and, therefore, cannot be universally adopted as a viable solution.
A third known approach involves using a redundant TSV for every signal TSV (100% redundancy). This scheme has no constraints, but is not a cost effective solution when there is a large array of TSVs like in memory-on-logic applications. A fourth approach involves a shift-right TSV redundancy architecture where there is one redundant TSV per row for an array of TSVs. This scheme has low TSV redundancy, but fails if there is more than one failing TSV in a single row.
A need therefore exists for methodology enabling a cost effective TSV redundancy architecture that has a low area overhead and can overcome issues of multiple fails in a single row or column in the TSV array and the resulting device.